1. Field
Aspects of the present invention relate to low power static random access memory.
2. Description of Related Art
Static random access memory (SRAM) is widely used in digital systems to provide memory for use with digital computers and other applications. SRAM has an advantage of high speed and ease of use as compared to some other types of memory systems. In addition, SRAM using MOS technology exhibits low standby power and does not require a refresh cycle to maintain the information stored.
SRAM systems are often organized into an array of SRAM cells, arranged in rows and columns. Generally, SRAM cells are set to one of two data states when storing a bit of information. Each memory cell may be referenced by a unique memory address, which includes a row address and a column address. The term “word line” refers to a conductor that corresponds to a row of SRAM cells, and the term “bit lines” refers to a set of conductors that correspond to a column of SRAM cells. The word line may be driven by a word line driver, and the bit lines may be driven by a bit line driver. A SRAM cell may include of pair of complementary ports, with each port coupled to one of the two bit lines corresponding to that column, two cross-coupled inverters to store a memory bit, and two access transistors to control access to the cross-coupled inverters.
SRAM arrays may operate in a read mode and a write mode. When reading from a SRAM cell, the bit lines associated with the SRAM cell are pre-charged to the high logic state, the corresponding word line is activated to read out the stored logic state, and the logic state is differentially sensed from the bit lines using a sense amplifier. The sense amplifier outputs a signal corresponding to the logic state stored in the SRAM, cell. When writing to a SRAM cell, the bits lines associated with the SRAM cell are complementarily driven to a logic state, the corresponding word line is activated to access the SRAM cell, and the SRAM cell is latched to a specific logic state, with a logic high indicated on one port and a logic low indicated on the other port.
In a SRAM array, the read and write cycles consume the majority of the power due to the discharge and charging operation of the bit lines. The frequency of operation, the working voltage, and the capacitance of each bit line are factors in determining the power consumed in each operation. The consumed power can be calculated as C*V2*F, where C is the capacitance of a bit line, V is the working voltage (i.e., the swing voltage of the bit line), and F is the frequency that a bit line is charged and discharged.